...
This commit is contained in:
@@ -0,0 +1 @@
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OBJS += mips/float_dsp_mips.o mips/cpu.o
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@@ -0,0 +1,108 @@
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/*
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* Copyright (c) 2015 Imagination Technologies Ltd
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||||
*
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||||
* This file is part of FFmpeg.
|
||||
*
|
||||
* FFmpeg is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* FFmpeg is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with FFmpeg; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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||||
*/
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||||
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/**
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* @file
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* MIPS assembly defines from sys/asm.h but rewritten for use with C inline
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* assembly (rather than from within .s files).
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*/
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#ifndef AVUTIL_MIPS_ASMDEFS_H
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#define AVUTIL_MIPS_ASMDEFS_H
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#include <stdint.h>
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#if defined(_ABI64) && _MIPS_SIM == _ABI64
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# define mips_reg int64_t
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# define PTRSIZE " 8 "
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# define PTRLOG " 3 "
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# define PTR_ADDU "daddu "
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# define PTR_ADDIU "daddiu "
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# define PTR_ADDI "daddi "
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# define PTR_SUBU "dsubu "
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# define PTR_L "ld "
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# define PTR_S "sd "
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# define PTR_SRA "dsra "
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# define PTR_SRL "dsrl "
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# define PTR_SLL "dsll "
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#else
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# define mips_reg int32_t
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# define PTRSIZE " 4 "
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# define PTRLOG " 2 "
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# define PTR_ADDU "addu "
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# define PTR_ADDIU "addiu "
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# define PTR_ADDI "addi "
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# define PTR_SUBU "subu "
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# define PTR_L "lw "
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# define PTR_S "sw "
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# define PTR_SRA "sra "
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# define PTR_SRL "srl "
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# define PTR_SLL "sll "
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#endif
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||||
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/*
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* parse_r var, r - Helper assembler macro for parsing register names.
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*
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* This converts the register name in $n form provided in \r to the
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* corresponding register number, which is assigned to the variable \var. It is
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* needed to allow explicit encoding of instructions in inline assembly where
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* registers are chosen by the compiler in $n form, allowing us to avoid using
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* fixed register numbers.
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*
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||||
* It also allows newer instructions (not implemented by the assembler) to be
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* transparently implemented using assembler macros, instead of needing separate
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* cases depending on toolchain support.
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*
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* Simple usage example:
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* __asm__ __volatile__("parse_r __rt, %0\n\t"
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* ".insn\n\t"
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* "# di %0\n\t"
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* ".word (0x41606000 | (__rt << 16))"
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* : "=r" (status);
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*/
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/* Match an individual register number and assign to \var */
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#define _IFC_REG(n) \
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".ifc \\r, $" #n "\n\t" \
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"\\var = " #n "\n\t" \
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".endif\n\t"
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__asm__(".macro parse_r var r\n\t"
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"\\var = -1\n\t"
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_IFC_REG(0) _IFC_REG(1) _IFC_REG(2) _IFC_REG(3)
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_IFC_REG(4) _IFC_REG(5) _IFC_REG(6) _IFC_REG(7)
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_IFC_REG(8) _IFC_REG(9) _IFC_REG(10) _IFC_REG(11)
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_IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
|
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_IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
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_IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
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_IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
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_IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
|
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".iflt \\var\n\t"
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".error \"Unable to parse register name \\r\"\n\t"
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".endif\n\t"
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".endm");
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|
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/* General union structure for clang adaption */
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union mmi_intfloat64 {
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int64_t i;
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double f;
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};
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#endif /* AVCODEC_MIPS_ASMDEFS_H */
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@@ -0,0 +1,134 @@
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/*
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||||
* This file is part of FFmpeg.
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||||
*
|
||||
* FFmpeg is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* FFmpeg is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with FFmpeg; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/cpu.h"
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#include "libavutil/cpu_internal.h"
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#include "config.h"
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#if defined __linux__ || defined __ANDROID__
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/auxv.h>
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#include "asmdefs.h"
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#include "libavutil/avstring.h"
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#endif
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#if defined __linux__ || defined __ANDROID__
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#define HWCAP_LOONGSON_CPUCFG (1 << 14)
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static int cpucfg_available(void)
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{
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return ff_getauxval(AT_HWCAP) & HWCAP_LOONGSON_CPUCFG;
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}
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/* Most toolchains have no CPUCFG support yet */
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static uint32_t read_cpucfg(uint32_t reg)
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{
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uint32_t __res;
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__asm__ __volatile__(
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"parse_r __res,%0\n\t"
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"parse_r reg,%1\n\t"
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||||
".insn \n\t"
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||||
".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t"
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:"=r"(__res)
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:"r"(reg)
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||||
:
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||||
);
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return __res;
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}
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#define LOONGSON_CFG1 0x1
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#define LOONGSON_CFG1_MMI (1 << 4)
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#define LOONGSON_CFG1_MSA1 (1 << 5)
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static int cpu_flags_cpucfg(void)
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{
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int flags = 0;
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uint32_t cfg1 = read_cpucfg(LOONGSON_CFG1);
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if (cfg1 & LOONGSON_CFG1_MMI)
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flags |= AV_CPU_FLAG_MMI;
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if (cfg1 & LOONGSON_CFG1_MSA1)
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flags |= AV_CPU_FLAG_MSA;
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return flags;
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}
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static int cpu_flags_cpuinfo(void)
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{
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FILE *f = fopen("/proc/cpuinfo", "r");
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char buf[200];
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int flags = 0;
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if (!f)
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return -1;
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while (fgets(buf, sizeof(buf), f)) {
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/* Legacy kernel may not export MMI in ASEs implemented */
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if (av_strstart(buf, "cpu model", NULL)) {
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||||
if (strstr(buf, "Loongson-3 "))
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flags |= AV_CPU_FLAG_MMI;
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||||
}
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||||
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||||
if (av_strstart(buf, "ASEs implemented", NULL)) {
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||||
if (strstr(buf, " loongson-mmi"))
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flags |= AV_CPU_FLAG_MMI;
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if (strstr(buf, " msa"))
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flags |= AV_CPU_FLAG_MSA;
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break;
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}
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}
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fclose(f);
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return flags;
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}
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#endif
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||||
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int ff_get_cpu_flags_mips(void)
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{
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#if defined __linux__ || defined __ANDROID__
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if (cpucfg_available())
|
||||
return cpu_flags_cpucfg();
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||||
else
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return cpu_flags_cpuinfo();
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||||
#else
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/* Assume no SIMD ASE supported */
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||||
return 0;
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||||
#endif
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||||
}
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||||
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||||
size_t ff_get_cpu_max_align_mips(void)
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||||
{
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||||
int flags = av_get_cpu_flags();
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|
||||
if (flags & AV_CPU_FLAG_MSA)
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return 16;
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|
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/*
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||||
* MMI itself is 64-bit but quad word load & store
|
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* needs 128-bit align.
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||||
*/
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||||
if (flags & AV_CPU_FLAG_MMI)
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return 16;
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||||
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||||
return 8;
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||||
}
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* This file is part of FFmpeg.
|
||||
*
|
||||
* FFmpeg is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* FFmpeg is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with FFmpeg; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef AVUTIL_MIPS_CPU_H
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#define AVUTIL_MIPS_CPU_H
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#include "libavutil/cpu.h"
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#include "libavutil/cpu_internal.h"
|
||||
|
||||
#define have_mmi(flags) CPUEXT(flags, MMI)
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||||
#define have_msa(flags) CPUEXT(flags, MSA)
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|
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#endif /* AVUTIL_MIPS_CPU_H */
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||||
@@ -0,0 +1,356 @@
|
||||
/*
|
||||
* Copyright (c) 2012
|
||||
* MIPS Technologies, Inc., California.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Author: Branimir Vasic (bvasic@mips.com)
|
||||
* Author: Zoran Lukic (zoranl@mips.com)
|
||||
*
|
||||
* This file is part of FFmpeg.
|
||||
*
|
||||
* FFmpeg is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* FFmpeg is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with FFmpeg; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Reference: libavutil/float_dsp.c
|
||||
*/
|
||||
|
||||
#include "config.h"
|
||||
#include "libavutil/float_dsp.h"
|
||||
#include "libavutil/mips/asmdefs.h"
|
||||
|
||||
#if HAVE_INLINE_ASM && HAVE_MIPSFPU
|
||||
#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
|
||||
static void vector_fmul_mips(float *dst, const float *src0, const float *src1,
|
||||
int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (len & 3) {
|
||||
for (i = 0; i < len; i++)
|
||||
dst[i] = src0[i] * src1[i];
|
||||
} else {
|
||||
float *d = (float *)dst;
|
||||
float *d_end = d + len;
|
||||
float *s0 = (float *)src0;
|
||||
float *s1 = (float *)src1;
|
||||
|
||||
float src0_0, src0_1, src0_2, src0_3;
|
||||
float src1_0, src1_1, src1_2, src1_3;
|
||||
|
||||
__asm__ volatile (
|
||||
"1: \n\t"
|
||||
"lwc1 %[src0_0], 0(%[s0]) \n\t"
|
||||
"lwc1 %[src1_0], 0(%[s1]) \n\t"
|
||||
"lwc1 %[src0_1], 4(%[s0]) \n\t"
|
||||
"lwc1 %[src1_1], 4(%[s1]) \n\t"
|
||||
"lwc1 %[src0_2], 8(%[s0]) \n\t"
|
||||
"lwc1 %[src1_2], 8(%[s1]) \n\t"
|
||||
"lwc1 %[src0_3], 12(%[s0]) \n\t"
|
||||
"lwc1 %[src1_3], 12(%[s1]) \n\t"
|
||||
"mul.s %[src0_0], %[src0_0], %[src1_0] \n\t"
|
||||
"mul.s %[src0_1], %[src0_1], %[src1_1] \n\t"
|
||||
"mul.s %[src0_2], %[src0_2], %[src1_2] \n\t"
|
||||
"mul.s %[src0_3], %[src0_3], %[src1_3] \n\t"
|
||||
"swc1 %[src0_0], 0(%[d]) \n\t"
|
||||
"swc1 %[src0_1], 4(%[d]) \n\t"
|
||||
"swc1 %[src0_2], 8(%[d]) \n\t"
|
||||
"swc1 %[src0_3], 12(%[d]) \n\t"
|
||||
PTR_ADDIU "%[s0], %[s0], 16 \n\t"
|
||||
PTR_ADDIU "%[s1], %[s1], 16 \n\t"
|
||||
PTR_ADDIU "%[d], %[d], 16 \n\t"
|
||||
"bne %[d], %[d_end], 1b \n\t"
|
||||
|
||||
: [src0_0]"=&f"(src0_0), [src0_1]"=&f"(src0_1),
|
||||
[src0_2]"=&f"(src0_2), [src0_3]"=&f"(src0_3),
|
||||
[src1_0]"=&f"(src1_0), [src1_1]"=&f"(src1_1),
|
||||
[src1_2]"=&f"(src1_2), [src1_3]"=&f"(src1_3),
|
||||
[d]"+r"(d), [s0]"+r"(s0), [s1]"+r"(s1)
|
||||
: [d_end]"r"(d_end)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
static void vector_fmul_scalar_mips(float *dst, const float *src, float mul,
|
||||
int len)
|
||||
{
|
||||
float temp0, temp1, temp2, temp3;
|
||||
float *local_src = (float*)src;
|
||||
float *end = local_src + len;
|
||||
|
||||
/* loop unrolled 4 times */
|
||||
__asm__ volatile(
|
||||
".set push \n\t"
|
||||
".set noreorder \n\t"
|
||||
"1: \n\t"
|
||||
"lwc1 %[temp0], 0(%[src]) \n\t"
|
||||
"lwc1 %[temp1], 4(%[src]) \n\t"
|
||||
"lwc1 %[temp2], 8(%[src]) \n\t"
|
||||
"lwc1 %[temp3], 12(%[src]) \n\t"
|
||||
PTR_ADDIU "%[dst], %[dst], 16 \n\t"
|
||||
"mul.s %[temp0], %[temp0], %[mul] \n\t"
|
||||
"mul.s %[temp1], %[temp1], %[mul] \n\t"
|
||||
"mul.s %[temp2], %[temp2], %[mul] \n\t"
|
||||
"mul.s %[temp3], %[temp3], %[mul] \n\t"
|
||||
PTR_ADDIU "%[src], %[src], 16 \n\t"
|
||||
"swc1 %[temp0], -16(%[dst]) \n\t"
|
||||
"swc1 %[temp1], -12(%[dst]) \n\t"
|
||||
"swc1 %[temp2], -8(%[dst]) \n\t"
|
||||
"bne %[src], %[end], 1b \n\t"
|
||||
" swc1 %[temp3], -4(%[dst]) \n\t"
|
||||
".set pop \n\t"
|
||||
|
||||
: [temp0]"=&f"(temp0), [temp1]"=&f"(temp1),
|
||||
[temp2]"=&f"(temp2), [temp3]"=&f"(temp3),
|
||||
[dst]"+r"(dst), [src]"+r"(local_src)
|
||||
: [end]"r"(end), [mul]"f"(mul)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static void vector_fmul_window_mips(float *dst, const float *src0,
|
||||
const float *src1, const float *win, int len)
|
||||
{
|
||||
float * dst_j, *win_j, *src0_i, *src1_j, *dst_i, *win_i;
|
||||
float temp, temp1, temp2, temp3;
|
||||
float s0, s01, s1, s11;
|
||||
float wi, wi1, wi2, wi3;
|
||||
float wj, wj1, wj2, wj3;
|
||||
const float * lp_end = win + len;
|
||||
|
||||
win_i = (float *)win;
|
||||
win_j = (float *)(win + 2 * len -1);
|
||||
src1_j = (float *)(src1 + len - 1);
|
||||
src0_i = (float *)src0;
|
||||
dst_i = (float *)dst;
|
||||
dst_j = (float *)(dst + 2 * len -1);
|
||||
|
||||
/* loop unrolled 4 times */
|
||||
__asm__ volatile (
|
||||
"1:"
|
||||
"lwc1 %[s1], 0(%[src1_j]) \n\t"
|
||||
"lwc1 %[wi], 0(%[win_i]) \n\t"
|
||||
"lwc1 %[wj], 0(%[win_j]) \n\t"
|
||||
"lwc1 %[s11], -4(%[src1_j]) \n\t"
|
||||
"lwc1 %[wi1], 4(%[win_i]) \n\t"
|
||||
"lwc1 %[wj1], -4(%[win_j]) \n\t"
|
||||
"lwc1 %[s0], 0(%[src0_i]) \n\t"
|
||||
"lwc1 %[s01], 4(%[src0_i]) \n\t"
|
||||
"mul.s %[temp], %[s1], %[wi] \n\t"
|
||||
"mul.s %[temp1], %[s1], %[wj] \n\t"
|
||||
"mul.s %[temp2], %[s11], %[wi1] \n\t"
|
||||
"mul.s %[temp3], %[s11], %[wj1] \n\t"
|
||||
"lwc1 %[s1], -8(%[src1_j]) \n\t"
|
||||
"lwc1 %[wi2], 8(%[win_i]) \n\t"
|
||||
"lwc1 %[wj2], -8(%[win_j]) \n\t"
|
||||
"lwc1 %[s11], -12(%[src1_j]) \n\t"
|
||||
"msub.s %[temp], %[temp], %[s0], %[wj] \n\t"
|
||||
"madd.s %[temp1], %[temp1], %[s0], %[wi] \n\t"
|
||||
"msub.s %[temp2], %[temp2], %[s01], %[wj1] \n\t"
|
||||
"madd.s %[temp3], %[temp3], %[s01], %[wi1] \n\t"
|
||||
"lwc1 %[wi3], 12(%[win_i]) \n\t"
|
||||
"lwc1 %[wj3], -12(%[win_j]) \n\t"
|
||||
"lwc1 %[s0], 8(%[src0_i]) \n\t"
|
||||
"lwc1 %[s01], 12(%[src0_i]) \n\t"
|
||||
PTR_ADDIU "%[src1_j],-16 \n\t"
|
||||
PTR_ADDIU "%[win_i],16 \n\t"
|
||||
PTR_ADDIU "%[win_j],-16 \n\t"
|
||||
PTR_ADDIU "%[src0_i],16 \n\t"
|
||||
"swc1 %[temp], 0(%[dst_i]) \n\t" /* dst[i] = s0*wj - s1*wi; */
|
||||
"swc1 %[temp1], 0(%[dst_j]) \n\t" /* dst[j] = s0*wi + s1*wj; */
|
||||
"swc1 %[temp2], 4(%[dst_i]) \n\t" /* dst[i+1] = s01*wj1 - s11*wi1; */
|
||||
"swc1 %[temp3], -4(%[dst_j]) \n\t" /* dst[j-1] = s01*wi1 + s11*wj1; */
|
||||
"mul.s %[temp], %[s1], %[wi2] \n\t"
|
||||
"mul.s %[temp1], %[s1], %[wj2] \n\t"
|
||||
"mul.s %[temp2], %[s11], %[wi3] \n\t"
|
||||
"mul.s %[temp3], %[s11], %[wj3] \n\t"
|
||||
"msub.s %[temp], %[temp], %[s0], %[wj2] \n\t"
|
||||
"madd.s %[temp1], %[temp1], %[s0], %[wi2] \n\t"
|
||||
"msub.s %[temp2], %[temp2], %[s01], %[wj3] \n\t"
|
||||
"madd.s %[temp3], %[temp3], %[s01], %[wi3] \n\t"
|
||||
"swc1 %[temp], 8(%[dst_i]) \n\t" /* dst[i+2] = s0*wj2 - s1*wi2; */
|
||||
"swc1 %[temp1], -8(%[dst_j]) \n\t" /* dst[j-2] = s0*wi2 + s1*wj2; */
|
||||
"swc1 %[temp2], 12(%[dst_i]) \n\t" /* dst[i+2] = s01*wj3 - s11*wi3; */
|
||||
"swc1 %[temp3], -12(%[dst_j]) \n\t" /* dst[j-3] = s01*wi3 + s11*wj3; */
|
||||
PTR_ADDIU "%[dst_i],16 \n\t"
|
||||
PTR_ADDIU "%[dst_j],-16 \n\t"
|
||||
"bne %[win_i], %[lp_end], 1b \n\t"
|
||||
: [temp]"=&f"(temp), [temp1]"=&f"(temp1), [temp2]"=&f"(temp2),
|
||||
[temp3]"=&f"(temp3), [src0_i]"+r"(src0_i), [win_i]"+r"(win_i),
|
||||
[src1_j]"+r"(src1_j), [win_j]"+r"(win_j), [dst_i]"+r"(dst_i),
|
||||
[dst_j]"+r"(dst_j), [s0] "=&f"(s0), [s01]"=&f"(s01), [s1] "=&f"(s1),
|
||||
[s11]"=&f"(s11), [wi] "=&f"(wi), [wj] "=&f"(wj), [wi2]"=&f"(wi2),
|
||||
[wj2]"=&f"(wj2), [wi3]"=&f"(wi3), [wj3]"=&f"(wj3), [wi1]"=&f"(wi1),
|
||||
[wj1]"=&f"(wj1)
|
||||
: [lp_end]"r"(lp_end)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static void butterflies_float_mips(float *restrict v1, float *restrict v2,
|
||||
int len)
|
||||
{
|
||||
float temp0, temp1, temp2, temp3, temp4;
|
||||
float temp5, temp6, temp7, temp8, temp9;
|
||||
float temp10, temp11, temp12, temp13, temp14, temp15;
|
||||
int pom;
|
||||
pom = (len >> 2)-1;
|
||||
|
||||
/* loop unrolled 4 times */
|
||||
__asm__ volatile (
|
||||
"lwc1 %[temp0], 0(%[v1]) \n\t"
|
||||
"lwc1 %[temp1], 4(%[v1]) \n\t"
|
||||
"lwc1 %[temp2], 8(%[v1]) \n\t"
|
||||
"lwc1 %[temp3], 12(%[v1]) \n\t"
|
||||
"lwc1 %[temp4], 0(%[v2]) \n\t"
|
||||
"lwc1 %[temp5], 4(%[v2]) \n\t"
|
||||
"lwc1 %[temp6], 8(%[v2]) \n\t"
|
||||
"lwc1 %[temp7], 12(%[v2]) \n\t"
|
||||
"beq %[pom], $zero, 2f \n\t"
|
||||
"1: \n\t"
|
||||
"sub.s %[temp8], %[temp0], %[temp4] \n\t"
|
||||
"add.s %[temp9], %[temp0], %[temp4] \n\t"
|
||||
"sub.s %[temp10], %[temp1], %[temp5] \n\t"
|
||||
"add.s %[temp11], %[temp1], %[temp5] \n\t"
|
||||
"sub.s %[temp12], %[temp2], %[temp6] \n\t"
|
||||
"add.s %[temp13], %[temp2], %[temp6] \n\t"
|
||||
"sub.s %[temp14], %[temp3], %[temp7] \n\t"
|
||||
"add.s %[temp15], %[temp3], %[temp7] \n\t"
|
||||
PTR_ADDIU "%[v1], %[v1], 16 \n\t"
|
||||
PTR_ADDIU "%[v2], %[v2], 16 \n\t"
|
||||
"addiu %[pom], %[pom], -1 \n\t"
|
||||
"lwc1 %[temp0], 0(%[v1]) \n\t"
|
||||
"lwc1 %[temp1], 4(%[v1]) \n\t"
|
||||
"lwc1 %[temp2], 8(%[v1]) \n\t"
|
||||
"lwc1 %[temp3], 12(%[v1]) \n\t"
|
||||
"lwc1 %[temp4], 0(%[v2]) \n\t"
|
||||
"lwc1 %[temp5], 4(%[v2]) \n\t"
|
||||
"lwc1 %[temp6], 8(%[v2]) \n\t"
|
||||
"lwc1 %[temp7], 12(%[v2]) \n\t"
|
||||
"swc1 %[temp9], -16(%[v1]) \n\t"
|
||||
"swc1 %[temp8], -16(%[v2]) \n\t"
|
||||
"swc1 %[temp11], -12(%[v1]) \n\t"
|
||||
"swc1 %[temp10], -12(%[v2]) \n\t"
|
||||
"swc1 %[temp13], -8(%[v1]) \n\t"
|
||||
"swc1 %[temp12], -8(%[v2]) \n\t"
|
||||
"swc1 %[temp15], -4(%[v1]) \n\t"
|
||||
"swc1 %[temp14], -4(%[v2]) \n\t"
|
||||
"bgtz %[pom], 1b \n\t"
|
||||
"2: \n\t"
|
||||
"sub.s %[temp8], %[temp0], %[temp4] \n\t"
|
||||
"add.s %[temp9], %[temp0], %[temp4] \n\t"
|
||||
"sub.s %[temp10], %[temp1], %[temp5] \n\t"
|
||||
"add.s %[temp11], %[temp1], %[temp5] \n\t"
|
||||
"sub.s %[temp12], %[temp2], %[temp6] \n\t"
|
||||
"add.s %[temp13], %[temp2], %[temp6] \n\t"
|
||||
"sub.s %[temp14], %[temp3], %[temp7] \n\t"
|
||||
"add.s %[temp15], %[temp3], %[temp7] \n\t"
|
||||
"swc1 %[temp9], 0(%[v1]) \n\t"
|
||||
"swc1 %[temp8], 0(%[v2]) \n\t"
|
||||
"swc1 %[temp11], 4(%[v1]) \n\t"
|
||||
"swc1 %[temp10], 4(%[v2]) \n\t"
|
||||
"swc1 %[temp13], 8(%[v1]) \n\t"
|
||||
"swc1 %[temp12], 8(%[v2]) \n\t"
|
||||
"swc1 %[temp15], 12(%[v1]) \n\t"
|
||||
"swc1 %[temp14], 12(%[v2]) \n\t"
|
||||
|
||||
: [v1]"+r"(v1), [v2]"+r"(v2), [pom]"+r"(pom), [temp0] "=&f" (temp0),
|
||||
[temp1]"=&f"(temp1), [temp2]"=&f"(temp2), [temp3]"=&f"(temp3),
|
||||
[temp4]"=&f"(temp4), [temp5]"=&f"(temp5), [temp6]"=&f"(temp6),
|
||||
[temp7]"=&f"(temp7), [temp8]"=&f"(temp8), [temp9]"=&f"(temp9),
|
||||
[temp10]"=&f"(temp10), [temp11]"=&f"(temp11), [temp12]"=&f"(temp12),
|
||||
[temp13]"=&f"(temp13), [temp14]"=&f"(temp14), [temp15]"=&f"(temp15)
|
||||
:
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static void vector_fmul_reverse_mips(float *dst, const float *src0, const float *src1, int len){
|
||||
int i;
|
||||
float temp0, temp1, temp2, temp3, temp4, temp5, temp6, temp7;
|
||||
src1 += len-1;
|
||||
|
||||
for(i=0; i<(len>>2); i++)
|
||||
{
|
||||
/* loop unrolled 4 times */
|
||||
__asm__ volatile(
|
||||
"lwc1 %[temp0], 0(%[src0]) \n\t"
|
||||
"lwc1 %[temp1], 0(%[src1]) \n\t"
|
||||
"lwc1 %[temp2], 4(%[src0]) \n\t"
|
||||
"lwc1 %[temp3], -4(%[src1]) \n\t"
|
||||
"lwc1 %[temp4], 8(%[src0]) \n\t"
|
||||
"lwc1 %[temp5], -8(%[src1]) \n\t"
|
||||
"lwc1 %[temp6], 12(%[src0]) \n\t"
|
||||
"lwc1 %[temp7], -12(%[src1]) \n\t"
|
||||
"mul.s %[temp0], %[temp1], %[temp0] \n\t"
|
||||
"mul.s %[temp2], %[temp3], %[temp2] \n\t"
|
||||
"mul.s %[temp4], %[temp5], %[temp4] \n\t"
|
||||
"mul.s %[temp6], %[temp7], %[temp6] \n\t"
|
||||
PTR_ADDIU "%[src0], %[src0], 16 \n\t"
|
||||
PTR_ADDIU "%[src1], %[src1], -16 \n\t"
|
||||
PTR_ADDIU "%[dst], %[dst], 16 \n\t"
|
||||
"swc1 %[temp0], -16(%[dst]) \n\t"
|
||||
"swc1 %[temp2], -12(%[dst]) \n\t"
|
||||
"swc1 %[temp4], -8(%[dst]) \n\t"
|
||||
"swc1 %[temp6], -4(%[dst]) \n\t"
|
||||
|
||||
: [dst]"+r"(dst), [src0]"+r"(src0), [src1]"+r"(src1),
|
||||
[temp0]"=&f"(temp0), [temp1]"=&f"(temp1),[temp2]"=&f"(temp2),
|
||||
[temp3]"=&f"(temp3), [temp4]"=&f"(temp4), [temp5]"=&f"(temp5),
|
||||
[temp6]"=&f"(temp6), [temp7]"=&f"(temp7)
|
||||
:
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
}
|
||||
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
|
||||
#endif /* HAVE_INLINE_ASM && HAVE_MIPSFPU */
|
||||
|
||||
void ff_float_dsp_init_mips(AVFloatDSPContext *fdsp) {
|
||||
#if HAVE_INLINE_ASM && HAVE_MIPSFPU
|
||||
#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
|
||||
fdsp->vector_fmul = vector_fmul_mips;
|
||||
fdsp->vector_fmul_scalar = vector_fmul_scalar_mips;
|
||||
fdsp->vector_fmul_window = vector_fmul_window_mips;
|
||||
fdsp->butterflies_float = butterflies_float_mips;
|
||||
fdsp->vector_fmul_reverse = vector_fmul_reverse_mips;
|
||||
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
|
||||
#endif /* HAVE_INLINE_ASM && HAVE_MIPSFPU */
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
|
||||
*
|
||||
* This file is part of FFmpeg.
|
||||
*
|
||||
* FFmpeg is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* FFmpeg is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with FFmpeg; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef AVUTIL_MIPS_INTREADWRITE_H
|
||||
#define AVUTIL_MIPS_INTREADWRITE_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "config.h"
|
||||
|
||||
#if ARCH_MIPS64 && HAVE_INLINE_ASM && !HAVE_MIPS64R6
|
||||
|
||||
#define AV_RN32 AV_RN32
|
||||
static av_always_inline uint32_t AV_RN32(const void *p)
|
||||
{
|
||||
struct __attribute__((packed)) u32 { uint32_t v; };
|
||||
const uint8_t *q = p;
|
||||
const struct u32 *pl = (const struct u32 *)(q + 3 * !HAVE_BIGENDIAN);
|
||||
const struct u32 *pr = (const struct u32 *)(q + 3 * HAVE_BIGENDIAN);
|
||||
uint32_t v;
|
||||
__asm__ ("lwl %0, %1 \n\t"
|
||||
"lwr %0, %2 \n\t"
|
||||
: "=&r"(v)
|
||||
: "m"(*pl), "m"(*pr));
|
||||
return v;
|
||||
}
|
||||
|
||||
#endif /* ARCH_MIPS64 && HAVE_INLINE_ASM && !HAVE_MIPS64R6 */
|
||||
|
||||
#endif /* AVUTIL_MIPS_INTREADWRITE_H */
|
||||
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2012
|
||||
* MIPS Technologies, Inc., California.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of the MIPS Technologies, Inc., nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Author: Nedeljko Babic (nbabic@mips.com)
|
||||
*
|
||||
* This file is part of FFmpeg.
|
||||
*
|
||||
* FFmpeg is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* FFmpeg is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with FFmpeg; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* MIPS optimization for some libm functions
|
||||
*/
|
||||
|
||||
#ifndef AVUTIL_MIPS_LIBM_MIPS_H
|
||||
#define AVUTIL_MIPS_LIBM_MIPS_H
|
||||
|
||||
#include "libavutil/attributes.h"
|
||||
|
||||
static av_always_inline av_const long int lrintf_mips(float x)
|
||||
{
|
||||
register int ret_int;
|
||||
|
||||
__asm__ volatile (
|
||||
"cvt.w.s %[x], %[x] \n\t"
|
||||
"mfc1 %[ret_int], %[x] \n\t"
|
||||
|
||||
:[x]"+f"(x), [ret_int]"=r"(ret_int)
|
||||
);
|
||||
return ret_int;
|
||||
}
|
||||
|
||||
#undef lrintf
|
||||
#define lrintf(x) lrintf_mips(x)
|
||||
|
||||
#define HAVE_LRINTF 1
|
||||
#endif /* AVUTIL_MIPS_LIBM_MIPS_H */
|
||||
@@ -0,0 +1,392 @@
|
||||
/*
|
||||
* Loongson SIMD utils
|
||||
*
|
||||
* Copyright (c) 2016 Loongson Technology Corporation Limited
|
||||
* Copyright (c) 2016 Zhou Xiaoyong <zhouxiaoyong@loongson.cn>
|
||||
*
|
||||
* This file is part of FFmpeg.
|
||||
*
|
||||
* FFmpeg is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2.1 of the License, or (at your option) any later version.
|
||||
*
|
||||
* FFmpeg is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with FFmpeg; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef AVUTIL_MIPS_MMIUTILS_H
|
||||
#define AVUTIL_MIPS_MMIUTILS_H
|
||||
|
||||
#include "config.h"
|
||||
|
||||
#include "libavutil/mem_internal.h"
|
||||
#include "libavutil/mips/asmdefs.h"
|
||||
|
||||
/*
|
||||
* These were used to define temporary registers for MMI marcos
|
||||
* however now we're using $at. They're theoretically unnecessary
|
||||
* but just leave them here to avoid mess.
|
||||
*/
|
||||
#define DECLARE_VAR_LOW32
|
||||
#define RESTRICT_ASM_LOW32
|
||||
#define DECLARE_VAR_ALL64
|
||||
#define RESTRICT_ASM_ALL64
|
||||
#define DECLARE_VAR_ADDRT
|
||||
#define RESTRICT_ASM_ADDRT
|
||||
|
||||
#if HAVE_LOONGSON2
|
||||
|
||||
#define MMI_LWX(reg, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
"lw "#reg", "#bias"($at) \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_SWX(reg, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
"sw "#reg", "#bias"($at) \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_LDX(reg, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
"ld "#reg", "#bias"($at) \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_SDX(reg, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
"sd "#reg", "#bias"($at) \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_LWC1(fp, addr, bias) \
|
||||
"lwc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_ULWC1(fp, addr, bias) \
|
||||
".set noat \n\t" \
|
||||
"ulw $at, "#bias"("#addr") \n\t" \
|
||||
"mtc1 $at, "#fp" \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_LWXC1(fp, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
MMI_LWC1(fp, $at, bias) \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_SWC1(fp, addr, bias) \
|
||||
"swc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_USWC1(fp, addr, bias) \
|
||||
".set noat \n\t" \
|
||||
"mfc1 $at, "#fp" \n\t" \
|
||||
"usw $at, "#bias"("#addr") \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_SWXC1(fp, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
MMI_SWC1(fp, $at, bias) \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_LDC1(fp, addr, bias) \
|
||||
"ldc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_ULDC1(fp, addr, bias) \
|
||||
".set noat \n\t" \
|
||||
"uld $at, "#bias"("#addr") \n\t" \
|
||||
"dmtc1 $at, "#fp" \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_LDXC1(fp, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
MMI_LDC1(fp, $at, bias) \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_SDC1(fp, addr, bias) \
|
||||
"sdc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_USDC1(fp, addr, bias) \
|
||||
".set noat \n\t" \
|
||||
"dmfc1 $at, "#fp" \n\t" \
|
||||
"usd $at, "#bias"("#addr") \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_SDXC1(fp, addr, stride, bias) \
|
||||
".set noat \n\t" \
|
||||
PTR_ADDU "$at, "#addr", "#stride" \n\t" \
|
||||
MMI_SDC1(fp, $at, bias) \
|
||||
".set at \n\t"
|
||||
|
||||
#define MMI_LQ(reg1, reg2, addr, bias) \
|
||||
"ld "#reg1", "#bias"("#addr") \n\t" \
|
||||
"ld "#reg2", 8+"#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_SQ(reg1, reg2, addr, bias) \
|
||||
"sd "#reg1", "#bias"("#addr") \n\t" \
|
||||
"sd "#reg2", 8+"#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_LQC1(fp1, fp2, addr, bias) \
|
||||
"ldc1 "#fp1", "#bias"("#addr") \n\t" \
|
||||
"ldc1 "#fp2", 8+"#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_SQC1(fp1, fp2, addr, bias) \
|
||||
"sdc1 "#fp1", "#bias"("#addr") \n\t" \
|
||||
"sdc1 "#fp2", 8+"#bias"("#addr") \n\t"
|
||||
|
||||
#elif HAVE_LOONGSON3 /* !HAVE_LOONGSON2 */
|
||||
|
||||
#define MMI_LWX(reg, addr, stride, bias) \
|
||||
"gslwx "#reg", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_SWX(reg, addr, stride, bias) \
|
||||
"gsswx "#reg", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_LDX(reg, addr, stride, bias) \
|
||||
"gsldx "#reg", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_SDX(reg, addr, stride, bias) \
|
||||
"gssdx "#reg", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_LWC1(fp, addr, bias) \
|
||||
"lwc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#if _MIPS_SIM == _ABIO32 /* workaround for 3A2000 gslwlc1 bug */
|
||||
|
||||
#define MMI_LWLRC1(fp, addr, bias, off) \
|
||||
".set noat \n\t" \
|
||||
"lwl $at, "#bias"+"#off"("#addr") \n\t" \
|
||||
"lwr $at, "#bias"("#addr") \n\t" \
|
||||
"mtc1 $at, "#fp" \n\t" \
|
||||
".set at \n\t"
|
||||
|
||||
#else /* _MIPS_SIM != _ABIO32 */
|
||||
|
||||
#define DECLARE_VAR_LOW32
|
||||
#define RESTRICT_ASM_LOW32
|
||||
|
||||
#define MMI_ULWC1(fp, addr, bias) \
|
||||
"gslwlc1 "#fp", 3+"#bias"("#addr") \n\t" \
|
||||
"gslwrc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#endif /* _MIPS_SIM != _ABIO32 */
|
||||
|
||||
#define MMI_LWXC1(fp, addr, stride, bias) \
|
||||
"gslwxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_SWC1(fp, addr, bias) \
|
||||
"swc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_USWC1(fp, addr, bias) \
|
||||
"gsswlc1 "#fp", 3+"#bias"("#addr") \n\t" \
|
||||
"gsswrc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_SWXC1(fp, addr, stride, bias) \
|
||||
"gsswxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_LDC1(fp, addr, bias) \
|
||||
"ldc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_ULDC1(fp, addr, bias) \
|
||||
"gsldlc1 "#fp", 7+"#bias"("#addr") \n\t" \
|
||||
"gsldrc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_LDXC1(fp, addr, stride, bias) \
|
||||
"gsldxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_SDC1(fp, addr, bias) \
|
||||
"sdc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_USDC1(fp, addr, bias) \
|
||||
"gssdlc1 "#fp", 7+"#bias"("#addr") \n\t" \
|
||||
"gssdrc1 "#fp", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_SDXC1(fp, addr, stride, bias) \
|
||||
"gssdxc1 "#fp", "#bias"("#addr", "#stride") \n\t"
|
||||
|
||||
#define MMI_LQ(reg1, reg2, addr, bias) \
|
||||
"gslq "#reg1", "#reg2", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_SQ(reg1, reg2, addr, bias) \
|
||||
"gssq "#reg1", "#reg2", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_LQC1(fp1, fp2, addr, bias) \
|
||||
"gslqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"
|
||||
|
||||
#define MMI_SQC1(fp1, fp2, addr, bias) \
|
||||
"gssqc1 "#fp1", "#fp2", "#bias"("#addr") \n\t"
|
||||
|
||||
#endif /* HAVE_LOONGSON2 */
|
||||
|
||||
/**
|
||||
* Backup saved registers
|
||||
* We're not using compiler's clobber list as it's not smart enough
|
||||
* to take advantage of quad word load/store.
|
||||
*/
|
||||
#define BACKUP_REG \
|
||||
LOCAL_ALIGNED_16(double, temp_backup_reg, [8]); \
|
||||
if (_MIPS_SIM == _ABI64) \
|
||||
__asm__ volatile ( \
|
||||
MMI_SQC1($f25, $f24, %[temp], 0x00) \
|
||||
MMI_SQC1($f27, $f26, %[temp], 0x10) \
|
||||
MMI_SQC1($f29, $f28, %[temp], 0x20) \
|
||||
MMI_SQC1($f31, $f30, %[temp], 0x30) \
|
||||
: \
|
||||
: [temp]"r"(temp_backup_reg) \
|
||||
: "memory" \
|
||||
); \
|
||||
else \
|
||||
__asm__ volatile ( \
|
||||
MMI_SQC1($f22, $f20, %[temp], 0x10) \
|
||||
MMI_SQC1($f26, $f24, %[temp], 0x10) \
|
||||
MMI_SQC1($f30, $f28, %[temp], 0x20) \
|
||||
: \
|
||||
: [temp]"r"(temp_backup_reg) \
|
||||
: "memory" \
|
||||
);
|
||||
|
||||
/**
|
||||
* recover register
|
||||
*/
|
||||
#define RECOVER_REG \
|
||||
if (_MIPS_SIM == _ABI64) \
|
||||
__asm__ volatile ( \
|
||||
MMI_LQC1($f25, $f24, %[temp], 0x00) \
|
||||
MMI_LQC1($f27, $f26, %[temp], 0x10) \
|
||||
MMI_LQC1($f29, $f28, %[temp], 0x20) \
|
||||
MMI_LQC1($f31, $f30, %[temp], 0x30) \
|
||||
: \
|
||||
: [temp]"r"(temp_backup_reg) \
|
||||
: "memory" \
|
||||
); \
|
||||
else \
|
||||
__asm__ volatile ( \
|
||||
MMI_LQC1($f22, $f20, %[temp], 0x10) \
|
||||
MMI_LQC1($f26, $f24, %[temp], 0x10) \
|
||||
MMI_LQC1($f30, $f28, %[temp], 0x20) \
|
||||
: \
|
||||
: [temp]"r"(temp_backup_reg) \
|
||||
: "memory" \
|
||||
);
|
||||
|
||||
/**
|
||||
* brief: Transpose 2X2 word packaged data.
|
||||
* fr_i0, fr_i1: src
|
||||
* fr_o0, fr_o1: dst
|
||||
*/
|
||||
#define TRANSPOSE_2W(fr_i0, fr_i1, fr_o0, fr_o1) \
|
||||
"punpcklwd "#fr_o0", "#fr_i0", "#fr_i1" \n\t" \
|
||||
"punpckhwd "#fr_o1", "#fr_i0", "#fr_i1" \n\t"
|
||||
|
||||
/**
|
||||
* brief: Transpose 4X4 half word packaged data.
|
||||
* fr_i0, fr_i1, fr_i2, fr_i3: src & dst
|
||||
* fr_t0, fr_t1, fr_t2, fr_t3: temporary register
|
||||
*/
|
||||
#define TRANSPOSE_4H(fr_i0, fr_i1, fr_i2, fr_i3, \
|
||||
fr_t0, fr_t1, fr_t2, fr_t3) \
|
||||
"punpcklhw "#fr_t0", "#fr_i0", "#fr_i1" \n\t" \
|
||||
"punpckhhw "#fr_t1", "#fr_i0", "#fr_i1" \n\t" \
|
||||
"punpcklhw "#fr_t2", "#fr_i2", "#fr_i3" \n\t" \
|
||||
"punpckhhw "#fr_t3", "#fr_i2", "#fr_i3" \n\t" \
|
||||
"punpcklwd "#fr_i0", "#fr_t0", "#fr_t2" \n\t" \
|
||||
"punpckhwd "#fr_i1", "#fr_t0", "#fr_t2" \n\t" \
|
||||
"punpcklwd "#fr_i2", "#fr_t1", "#fr_t3" \n\t" \
|
||||
"punpckhwd "#fr_i3", "#fr_t1", "#fr_t3" \n\t"
|
||||
|
||||
/**
|
||||
* brief: Transpose 8x8 byte packaged data.
|
||||
* fr_i0~i7: src & dst
|
||||
* fr_t0~t3: temporary register
|
||||
*/
|
||||
#define TRANSPOSE_8B(fr_i0, fr_i1, fr_i2, fr_i3, fr_i4, fr_i5, \
|
||||
fr_i6, fr_i7, fr_t0, fr_t1, fr_t2, fr_t3) \
|
||||
"punpcklbh "#fr_t0", "#fr_i0", "#fr_i1" \n\t" \
|
||||
"punpckhbh "#fr_t1", "#fr_i0", "#fr_i1" \n\t" \
|
||||
"punpcklbh "#fr_t2", "#fr_i2", "#fr_i3" \n\t" \
|
||||
"punpckhbh "#fr_t3", "#fr_i2", "#fr_i3" \n\t" \
|
||||
"punpcklbh "#fr_i0", "#fr_i4", "#fr_i5" \n\t" \
|
||||
"punpckhbh "#fr_i1", "#fr_i4", "#fr_i5" \n\t" \
|
||||
"punpcklbh "#fr_i2", "#fr_i6", "#fr_i7" \n\t" \
|
||||
"punpckhbh "#fr_i3", "#fr_i6", "#fr_i7" \n\t" \
|
||||
"punpcklhw "#fr_i4", "#fr_t0", "#fr_t2" \n\t" \
|
||||
"punpckhhw "#fr_i5", "#fr_t0", "#fr_t2" \n\t" \
|
||||
"punpcklhw "#fr_i6", "#fr_t1", "#fr_t3" \n\t" \
|
||||
"punpckhhw "#fr_i7", "#fr_t1", "#fr_t3" \n\t" \
|
||||
"punpcklhw "#fr_t0", "#fr_i0", "#fr_i2" \n\t" \
|
||||
"punpckhhw "#fr_t1", "#fr_i0", "#fr_i2" \n\t" \
|
||||
"punpcklhw "#fr_t2", "#fr_i1", "#fr_i3" \n\t" \
|
||||
"punpckhhw "#fr_t3", "#fr_i1", "#fr_i3" \n\t" \
|
||||
"punpcklwd "#fr_i0", "#fr_i4", "#fr_t0" \n\t" \
|
||||
"punpckhwd "#fr_i1", "#fr_i4", "#fr_t0" \n\t" \
|
||||
"punpcklwd "#fr_i2", "#fr_i5", "#fr_t1" \n\t" \
|
||||
"punpckhwd "#fr_i3", "#fr_i5", "#fr_t1" \n\t" \
|
||||
"punpcklwd "#fr_i4", "#fr_i6", "#fr_t2" \n\t" \
|
||||
"punpckhwd "#fr_i5", "#fr_i6", "#fr_t2" \n\t" \
|
||||
"punpcklwd "#fr_i6", "#fr_i7", "#fr_t3" \n\t" \
|
||||
"punpckhwd "#fr_i7", "#fr_i7", "#fr_t3" \n\t"
|
||||
|
||||
/**
|
||||
* brief: Parallel SRA for 8 byte packaged data.
|
||||
* fr_i0: src
|
||||
* fr_i1: SRA number(SRAB number + 8)
|
||||
* fr_t0, fr_t1: temporary register
|
||||
* fr_d0: dst
|
||||
*/
|
||||
#define PSRAB_MMI(fr_i0, fr_i1, fr_t0, fr_t1, fr_d0) \
|
||||
"punpcklbh "#fr_t0", "#fr_t0", "#fr_i0" \n\t" \
|
||||
"punpckhbh "#fr_t1", "#fr_t1", "#fr_i0" \n\t" \
|
||||
"psrah "#fr_t0", "#fr_t0", "#fr_i1" \n\t" \
|
||||
"psrah "#fr_t1", "#fr_t1", "#fr_i1" \n\t" \
|
||||
"packsshb "#fr_d0", "#fr_t0", "#fr_t1" \n\t"
|
||||
|
||||
/**
|
||||
* brief: Parallel SRL for 8 byte packaged data.
|
||||
* fr_i0: src
|
||||
* fr_i1: SRL number(SRLB number + 8)
|
||||
* fr_t0, fr_t1: temporary register
|
||||
* fr_d0: dst
|
||||
*/
|
||||
#define PSRLB_MMI(fr_i0, fr_i1, fr_t0, fr_t1, fr_d0) \
|
||||
"punpcklbh "#fr_t0", "#fr_t0", "#fr_i0" \n\t" \
|
||||
"punpckhbh "#fr_t1", "#fr_t1", "#fr_i0" \n\t" \
|
||||
"psrlh "#fr_t0", "#fr_t0", "#fr_i1" \n\t" \
|
||||
"psrlh "#fr_t1", "#fr_t1", "#fr_i1" \n\t" \
|
||||
"packsshb "#fr_d0", "#fr_t0", "#fr_t1" \n\t"
|
||||
|
||||
#define PSRAH_4_MMI(fp1, fp2, fp3, fp4, shift) \
|
||||
"psrah "#fp1", "#fp1", "#shift" \n\t" \
|
||||
"psrah "#fp2", "#fp2", "#shift" \n\t" \
|
||||
"psrah "#fp3", "#fp3", "#shift" \n\t" \
|
||||
"psrah "#fp4", "#fp4", "#shift" \n\t"
|
||||
|
||||
#define PSRAH_8_MMI(fp1, fp2, fp3, fp4, fp5, fp6, fp7, fp8, shift) \
|
||||
PSRAH_4_MMI(fp1, fp2, fp3, fp4, shift) \
|
||||
PSRAH_4_MMI(fp5, fp6, fp7, fp8, shift)
|
||||
|
||||
/**
|
||||
* brief: (((value) + (1 << ((n) - 1))) >> (n))
|
||||
* fr_i0: src & dst
|
||||
* fr_i1: Operand number
|
||||
* fr_t0, fr_t1: temporary FPR
|
||||
* gr_t0: temporary GPR
|
||||
*/
|
||||
#define ROUND_POWER_OF_TWO_MMI(fr_i0, fr_i1, fr_t0, fr_t1, gr_t0) \
|
||||
"li "#gr_t0", 0x01 \n\t" \
|
||||
"dmtc1 "#gr_t0", "#fr_t0" \n\t" \
|
||||
"punpcklwd "#fr_t0", "#fr_t0", "#fr_t0" \n\t" \
|
||||
"psubw "#fr_t1", "#fr_i1", "#fr_t0" \n\t" \
|
||||
"psllw "#fr_t1", "#fr_t0", "#fr_t1" \n\t" \
|
||||
"paddw "#fr_i0", "#fr_i0", "#fr_t1" \n\t" \
|
||||
"psraw "#fr_i0", "#fr_i0", "#fr_i1" \n\t"
|
||||
|
||||
#endif /* AVUTILS_MIPS_MMIUTILS_H */
|
||||
Reference in New Issue
Block a user